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rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 1 of 35 X80000/x80001 features integrates three major functions smart power plug communications programmable power sequencing programmable hot swap controller smart power plug tm intelligent board insertion allows veri?ation of board and power supply resources prior to system insertion. fault detection register records the cause of the faults soft extraction soft re-insertion remote gate shutdown/turn on power id/manufacturing id memory (2kb of eeprom) programmable power sequencing sequence up to 5 dc/dc converters. four independent voltage enable pins four programmable time delay circuits soft power sequencing - restart sequence without power cycling. hot swap controller programmable overvoltage and undervoltage protection undervoltage lockout for battery/redundant supplies programmable slew rate for external fet gate control electronic circuit breaker - overcurrent detection and gate shut-off programmable overcurrent limit during insertion programmable hardshort retry with retry failure ?g typically operates from -30v to -80v. tolerates transients to -200v (limited by external components) available packages 32-lead quad no-lead frame (qfn) applications -48v hot swap power backplane/distribution central of?e, ethernet for voip card insertion detection power sequencing dc-dc/power bricks ip phone applications databus power interfacing custom industrial power backplanes distributed power systems description the X80000 contains three major functions: a power communications controller, a power sequencing controller, and a hotswap controller. the power communications controller allows smart power supply control via the backplane using the smbus protocol. the system can check for voltage, current, and manu- facturing id compliance before board insertion. the power distribution network can monitor the status of the negative voltage supply, dc voltage supplies, and hardshort events by accessing the fault detection register and general purpose eeprom of the device. each device has a unique slave address for identi?ation. the power sequencer controller time sequences up to ?e dc- dc modules. the X80000 allows for various hardwired con?urations, either parallel or relay sequencing modes. the power good, enable and voltage good signals provide for ?xible dc-dc timing con?urations. each voltage enable signal has a programmable delay. in addition, the voltage good signals can be monitored remotely via the fault detection register (thru the smbus). new industry features programmable power sequencing modes battery backup mode programmable hardshort retry programmable overcurrent five power good signals smart power plug tm penta-power sequence controller with hot swap typical application v dd X80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 rtn 100k v1good v2good v3good dc-dc module 1 on /off dc-dc module 2 on /off dc-dc module 3 on /off dc-dc module 4 on /off pwrgd en1 en2 en3 scl scl 4.7v 12v x80001 v1 v2 v3 v4 100 0.1uf sda back- plane sda mrh opto- isolation insert control
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 2 of 35 X80000/x80001 ?preliminary information ordering information v1good mrc a0 v3good v2good en4 en3 en1 reset wp v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd f ar batt-on mrh i gq1 scl 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 sda en2 817 nc v ee 15 25 v rgo 16 a1 nc nc qfn package (top view) (7mm x 7mm) order number ov uv1 uv2 temp range package part mark X80000q32i 74.9 42.4 33.2 i qfn 80000i x80001q32i 68.0 42.4 33.2 i qfn 80001i absolute maximum ratings temperature under bias ............................. ?5? to +135? storage temperature .................................. ?5? to +150? voltage on given pin (hot side functions): v ov / uv pin ............................................................5.5v + v ee sense pin .......................................................400mv + v ee v ee pin...........................................................................-80v drain pin .............................................................48v + v ee pwrgd pin ............................................................7v + v ee gate pin.............................................................. v dd + v ee f ar pin ...................................................................7v + v ee mrh pin ...............................................................5.5v + v ee batt_on pin .......................................................5.5v + v ee voltage on given pin (cold side functions): eni pins (i = 1 to 4)............................................................ 5v vigood pins (i = 1 to 4) .....................................5.5v + v ee reset pin ...........................................................5.5v + v ee sda, scl, wp, a0, a1 pins..................................5.5v + v ee mrc pin ...............................................................5.5v + v ee igq1 and igq0 pins ............................................5.5v + v ee v dd pin .................................................................14v + v ee d.c. output current ......................................................... 5ma lead temperature (soldering, 10 seconds) ................. 300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. industrial (i) ?0? +85? supply voltage v dd = 12v description (continued) the hot swap controller allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. the X80000 family of devices offers a modular, power distribution approach by providig ?xibility to solve the hotswap and power sequencing issues for insertion, operations, and extraction. hardshort detection and retry with delay, noise ?tering, insertion overcurrent bypass, and gate current selection are some of the programmable features of the device. during insertion, the gate of an external power mosfet is clamped low to suppress contact bounce. the under-voltage/ over-voltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. the X80000 turns on the gate with a user set slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. after the load is successfully charged, the pwrgd signal is asserted; indicating that the device is ready to power sequence the dc-dc power bricks.
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 3 of 35 X80000/x80001 ?preliminary information electrical characteristics (standard settings) (over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions dc characteristics v dd supply operating range 10 12 14 v i dd supply current 2.5 5 ma v rgo regulated 5v output 4.5 5.5 i rgo =10ua i rgo v rgo current output 50 ? i gate gate pin current 46.2 52.5 58.8 ? gate drive on, v gate = v ee , v sense = v ee (sourcing) 9mav gate - v ee = 3v v sense -v ee = 0.1v (sinking) v gate external gate drive (slew rate control) v dd -0.01 v dd vi gate = 50ua v pga power good threshold (pwrgd high to low) 0.9 1 1.1 v referenced to v ee v uv1 < v uv/ov < v ov v ihb voltage input high (batt_on) v ee + 4 v ee + 5 v v ilb voltage input low (batt_on) v ee + 2 v i li input leakage current (mrh , mrc) 10 ? v il = gnd to v cc i lo output leakage current (v1good , v2good , v3good , v4good , reset ) 10 ? all eni = v rgo for i = 1 to 4 v il input low voltage (mrh , mrc, igq0, igq1) -0.5 + v ee (v ee + 5) x 0.3 v v ih input high voltage (mrh , mrc, igq0, igq1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v v ol output low voltage (reset , v1good , v2good , v3good , v4good, far , pwrgd ) v ee + 0.4 v i ol = 4.0 ma c out (1) output capacitance (reset , v1good , v2good , v3good , v4good , far ) 8pfv out = 0v c in (1) input capacitance (mrh , mrc) 6 pf v in = 0v v oc over-current threshold 45 50 55 mv v oc = v sense - v ee v oci over-current threshold (insertion) 135 150 165 mv v oc = v sense - v ee pwrgd = high initial power up condition v ovr overvoltage threshold (rising) X80000 x80001 3.85 3.49 3.90 3.54 3.95 3.59 v referenced to v ee v ovf overvoltage threshold (falling) X80000 x80001 3.82 3.46 3.87 3.51 3.92 3.56 v referenced to v ee v uv1r undervoltage 1 threshold (rising) 2.19 2.24 2.29 v referenced to v ee batt-on = v ee v uv1f undervoltage 1 threshold (falling) 2.16 2.21 2.26 v v uv2r undervoltage 2 threshold (rising) 1.71 1.76 1.81 v referenced to v ee batt-on = v rgo v uv2f undervoltage 2 threshold (falling) 1.68 1.73 1.78 v
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 4 of 35 X80000/x80001 ?preliminary information notes: (1) this parameter is based on characterization data. v drainf drain sense voltage threshold (falling) 0.9 1 1.1 v referenced to v ee v drainr drain sense voltage threshold (rising) 1.2 1.3 1.4 v referenced to v ee v trip1 en1 trip point voltage 2.25 2.5 2.75 v referenced to v ee v trip2 en2 trip point voltage 2.25 2.5 2.75 v referenced to v ee v trip3 en3 trip point voltage 2.25 2.5 2.75 v referenced to v ee v trip4 en4 trip point voltage 2.25 2.5 2.75 v referenced to v ee ac characteristics t foc sense high to gate low 1.5 2.5 3.5 s t fuv under voltage conditions to gate low 0.5 1 1.5 s t fov overvoltage conditions to gate low 1.0 1.5 2 s t vfr overvoltage/undervoltage failure recovery time to gate =1v. 1.2 1.6 2 sv dd does not drop below 3v, no other failure conditions. t batt_on delay batt_on valid 100 ns t mrc minimum time high for reset valid on the mrc pin 5 s t mrh minimum time high for reset valid on the mrh pin 5 s t mrce delay from mrc enable to pwrgd high 1.0 1.6 s no load t mrcd delay from mrc disable to pwrgd low 200 400 ns gate is on, no load t mrhe delay from mrh enable to gate pin low 1.0 1.6 2.4 si gate = 60?, no load t mrhd delay from mrh disable to gate reaching 1v 1.8 2.6 si gate = 60?, no load t reset _e delay from pwrgd or vigood to reset valid low 1 s t qc delay from igq1 and igq0 to valid gate pin current 1 s t sc_retry delay between retries 90 100 110 ms tsc1 = 0; tsc0 = 0 t nf noise filter for overcurrent 4.5 5 5.5 ? tf1 = 0; tf0 = 1 t dpor device delay before gate assertion 45 50 55 ms t spor delay after pwrgd and all vigood signals are active before reset assertion 90 100 110 ms tpor1 = 0; tpor0 = 0 t delay1 t delay2 t delay3 t delay4 power sequencing time delay 90 100 110 ms tid1 = 0; tid0 = 0 t to vigood turn off time 50 ns electrical characteristics (continued)(standard settings) (over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 5 of 35 X80000/x80001 ?preliminary information equivalent a.c. output load circuit a.c. test conditions figure 1. overvoltage/undervoltage gate timing figure 2. overcurrent gate timing 5v sda 30pf 4.6k ? reset 30pf v1good , 5v 4.6k ? 30pf v2good , v3good , v4good , far 5v 4.6k ? pwrgd input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sense v uv/ov v ov v uv v dd v th mrh gate v oc v oci t vfr t fov t fuv t dpor t vfr 1v 1v sense v dd v th gate v oc v oci t dpor t sc_retry t foc t foc always retry v uv < v uv/ov < v ov t sc_retry mrh = high
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 6 of 35 X80000/x80001 ?preliminary information figure 3. vigood timings figure 4. manual reset (hot side) mrh figure 5. manual reset (cold side) mrc eni t to vigood v tripi t delayi i = 1, 2, 3, 4 initial power-up t to v dd enable dc/dc supply t mrhd gate t mrhe mrh t mrh 1v t mrcd pwrgd mrc t mrce t mrc figure 6. reset timings pwrgd t delay1 v1good t delay2 v2good t delay3 v3good t delay4 v4good t spor reset t reset _e pwrgd or any vigood v drain t phlpg t plhpg (1st occurance)
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 7 of 35 X80000/x80001 ?preliminary information electrical characteristics (programmable parameters) (over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions dc characteristics v cb over current trip voltage range (v cb = v sense - v ee ) 30 100 mv factory setting is 50mv (see v oci ). for other options, contact xicor. i gate gate pin pull-up current. (error) (current) ig3 = 0; ig2= 0; ig1 = 0; ig0 = 0 ig3 = 0; ig2= 0; ig1 = 0; ig0 = 1 ig3 = 0; ig2= 0; ig1 = 1; ig0 = 0 ig3 = 0; ig2= 0; ig1 = 1; ig0 = 1 ig3 = 0; ig2= 1; ig1 = 0; ig0 = 0 ig3 = 0; ig2= 1; ig1 = 0; ig0 = 1 ig3 = 0; ig2= 1; ig1 = 1; ig0 = 0 ig3 = 0; ig2= 1; ig1 = 1; ig0 = 1 ig3 = 1; ig2= 0; ig1 = 0; ig0 = 0 ig3 = 1; ig2= 0; ig1 = 0; ig0 = 1 ig3 = 1; ig2= 0; ig1 = 1; ig0 = 0 ig3 = 1; ig2= 0; ig1 = 1; ig0 = 1 ig3 = 1; ig2= 1; ig1 = 0; ig0 = 0 ig3 = 1; ig2= 1; ig1 = 0; ig0 = 1 ig3 = 1; ig2= 1; ig1 = 1; ig0 = 0 ig3 = 1; ig2= 1; ig1 = 1; ig0 = 1 ig3-ig0 = don? care ig3-ig0 = don? care ig3-ig0 = don? care -12 9.2 46.2 64.7 138.6 9.2 64.7 138.6 10.5 21.0 31.5 42.0 52.5 63.0 73.5 84.0 94.5 105.0 115.5 126.0 136.5 147.0 157.5 168.0 10.57 73.5 157.5 +12 11.8 58.5 82.3 176.4 11.8 82.3 176.4 % ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gate drive on; v gate = v ee , igq1=0; igq0=0 factory default igq1=0; igq0=1 igq1=1; igq0=0 igq1=1; igq0=1 v pga power good threshold accuracy ?00 mv v drain - v ee , high to low transi- tion. default factory setting is 47v. v oci over current threshold (insertion) vs1 = 0 vs0 = 0 vs1 = 0 vs0 = 1 vs1 = 1 vs0 = 0 vs1 = 1 vs0 = 1 45 90 135 180 50 100 150 200 55 110 165 220 mv mv mv mv referenced to v ee pwrgd = high factory default ac characteristics t sc_retry delay between retries tsc1 = 0 tsc0 = 0 tsc1 = 0 tsc0 = 1 tsc1 = 1 tsc0 = 0 tsc1 = 1 tsc0 = 1 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s factory default
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 8 of 35 X80000/x80001 ?preliminary information t nf noise filter for overcurrents f1 = 0 f0 = 0 f1 = 0 f0 = 1 f1 = 1 f0 = 0 f1 = 1 f0 = 1 4.5 9 18 0 5 10 20 5.5 11 22 ? ? ? ? factory default t spor delay before reset assertion tpor1 = 0 tpor0 = 0 tpor1 = 0 tpor0 = 1 tpor1 = 1 tpor0 = 0 tpor1 = 1 tpor0 = 1 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s factory default t delayi time delay used in power sequencing (i = 1 to 4) tid1 = 0 tid0 = 0 tid1 = 0 tid0 = 1 tid1 = 1 tid0 = 0 tid1 = 1 tid0 = 1 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s factory default electrical characteristics (continued)(programmable parameters) (over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions serial interface ( over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions dc characteristics i cc1 (1) active supply current ( v dd ) read to memory or crs 2.5 ma v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz i cc2 (1) active supply current ( v dd ) write to memory or crs 3.0 ma i li input leakage current (scl, wp, a0, a1) 10 ? v il = gnd to v cc i lo output leakage current (sda) 10 ? v sda = gnd to v cc device is in standby (2) v il (3) input low voltage (sda, scl, wp, a0, a1) -0.5 + vee (v ee + 5) x 0.3 v v ih (3) input high voltage (sda, scl, wp, a0, a1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v v hys schmitt trigger input hysteresis ?fixed input level ?v cc related level v ee + 0.2 .05 x (v ee + 5) v v v ol output low voltage (sda) v ee + 0.4 v i ol = 4.0 ma (2.7-5.5v) i ol = 2.0 ma (2.4-3.6v) ac characteristics f scl scl clock frequency 400 khz t in pulse width suppression time at in- puts 50 ns t aa scl low to sda data out valid 0.1 1.5 ? t buf time the bus is free before start of new transmission 1.3 ? t low clock low time 1.3 ? t high clock high time 0.6 ?
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 9 of 35 X80000/x80001 ?preliminary information timing diagrams figure 7. bus timing figure 8. wp pin timing t su:sta start condition setup time 0.6 ? t hd:sta start condition hold time 0.6 ? t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 ? t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1) 300 ns t f sda and scl fall time 20 +.1cb (1) 300 ns t su:wp wp setup time 0.6 ? t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf t wc (2) eeprom write cycle time 5 10 ms note: (2) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. serial interface (continued) ( over the recommended operating conditions unless otherwise speci?d). symbol parameter min. typ. max. unit test conditions t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t r t dh t aa t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 10 of 35 X80000/x80001 ?preliminary information figure 9. write cycle timing symbol table scl sda t wc 8 th bit of last byte ack stop condition start condition must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known waveform inputs outputs to high
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 11 of 35 X80000/x80001 ?preliminary information typical performance characteristics over current threshold vs. temperature overvoltage threshold vs. temperature undervoltage 1 threshold vs. temperature undervoltage 2 threshold vs. temperature eni threshold vs. temperature i gate (source) vs. temperature 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature inrush current limit (mv) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling ov threshold (v) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 1 threshold (v) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 2 threshold (v) 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature eni threshold (v) 0 40 80 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature 150? 70? 50? 10? gate current (?)
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 12 of 35 X80000/x80001 ?preliminary information i gate (sink) vs. temperature t fuv vs. temperature t fov vs. temperature t foc vs. temperature t delayi vs. temperature 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature gate current - sink (ma) 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature tuv1 tuv2 t uv (?) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t ov (?) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t oc (?) 0.90 0.92 0.94 0.96 0.98 1.00 1.02 -55 -35 -15 5 25 45 65 85 temperature t delay (normalized)
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 13 of 35 X80000/x80001 ?preliminary information figure 10.block diagram sense v ee gate igq1 igq0 drain batt-on mrc mrh en1 en2 en3 en4 v4good v3good v2good v1good a1 a2 wp scl sda reset v dd f ar pwrgd power good logic slew rate selection eeprom 2kbits delay logic enable logic 5v reg. v rgo bus interface v ee v ee v ee v ee v ee v ee v ov ref v uv1 ref v uv2 ref v uv/ov 2:1 mux v ee gate control v dd 1v ref v trip1 v trip2 v trip3 v trip4 v rgo programmable v oc ref 36r rrrr over current select x1 x2 x3 x4 reset logic and delay v ee over current logic, hard short relay, retry logic status and delay time delay 1 time delay 2 time delay 3 time delay 4 por control and fault registers 10-160ua
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 14 of 35 X80000/x80001 ?preliminary information pin configuration pin descriptions pin name description 1v rgo regulated 5v output. used to pull-up user programmable inputs igq0, igq1, batt-on, a1, a0, and wp (if needed). 2a0 address select input. it has an internal pulldown resistor. (>10m ? typical) the a0 and a1 bits allow for up to 4 X80000 devices to be used on the same smbus serial interface. 3 v4good v4 voltage good output. this open drain output goes low when en4 is less than v trip4 and goes high when en4 is great- er than v trip4 . there is a user selectable delay circuitry on this pin. 4 en4 v4 voltage enable input. fourth voltage enable pin. if unused connect to v rgo . 5 v3good v3 voltage good output (active low). this open drain output goes low when en3 is less than v trip3 and goes high when en3 is greater than v trip3 . there is a user selectable delay circuitry on this pin. 6 en3 v3 voltage enable input. third voltage enable pin. if unused connect to v rgo . 7 v2good v2 voltage good output (active low). this open drain output goes low when en2 is less than v trip2 and goes high when en2 is greater than v trip2 . there is a user selectable delay circuitry on this pin. 8 en2 v2 voltage enable input. second voltage enable pin. if unused connect to v rgo . 9v dd positive supply voltage input. v1good mrc a0 v3good v2good en4 en3 en1 reset wp v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd f ar batt-on mrh i gq1 scl 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 X80000/x80001 32-lead qfn quad package sda en2 817 na v ee 15 25 v rgo 16 a1 nc nc (7mm x 7mm) 10 v ee negative supply voltage input. 11 v uv/ov analog undervoltage and overvoltage input. turns off the external n-channel mosfet when there is an undervoltage or overvoltage condition. 12 sense circuit breaker sense input . this input pin detects the overcurrent condition. 13 gate gate drive output. gate drive output for the external n-channel mosfet. 14 drain drain . drain sense input of the external n- channel mosfet. 15 na not available. do not connect to this pin. 16 a1 address select input. it has an internal pulldown resistor. (>10m ? typical) the a0 and a1 bits allow for up to 4 X80000 devices to be used on the same smbus serial interface. 17 sda serial data. sda is a bidirectional pin used to transfer data into and out of the de- vice. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is al- ways active (not gated). 18 scl serial clock. the serial clock controls the serial bus timing for data input and output. 19 en1 v1 voltage enable input. first voltage en- able pin. if unused connect to v rgo . 20 v1good v1 voltage good output (active low). this open drain output goes low when en1 is less than v trip1 and goes high when en1 is greater than v trip1 . there is a user selectable delay circuitry on this pin. 21 reset reset output. this open drain pin is an active low output . this pin will be active unitl pwrgd goes active and the power sequencing is complete. this pin will be re- leased after a programmable delay. 22 wp write protect. input pin. wp high (in conjunction with wpen bit=1) prevents writes to any memory location in the device. it has an internal pulldown resistor. (>10m ? typical) 23 mrc manual reset input cold-side. pulling the mrc pin high initiates a system side reset. the mrc signal must be held high for 5 secs. it has an internal pull- down resistor. (>10m ? typical) 24 nc no connect. no internal connections. 25 v ee negative supply voltage input. 26 nc no connect. no internal connections. pin name description
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 15 of 35 X80000/x80001 ?preliminary information principles of operation hot circuit insertion when circuit boards are inserted into a live backplane, the bypass capacitors at the input of the boards power module or dc/dc converter can draw huge transient currents as they charge up. see figure 11. this transient current can cause permanent damage to the boards components and cause transients on the system power supply. the X80000 is designed to turn on a boards supply voltage in a controlled manner (see figure 12), allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (dc-dc converter) off until the backplane input voltage is stable and within tolerance. over-voltage and under-voltage shutdown the X80000 provides over-voltage and under-voltage protection circuits. when an over-voltage (v ov ) or under-voltage (v uv1 and v uv2 ) condition is detected, the gate pin will be immediately pulled low. the under-voltage threshold v uv1 applies to the normal operation with a main supply. the under-voltage threshold v uv2 assumes the system is powered by a battery. when using a battery backup, the batt-on pin is pulled to v rgo . the default thresholds have been set so the external resistance values determine the overvoltage threshold, a main undervoltage threshold and a battery undervoltage threshold. for information on over-voltage and under-voltage fault monitoring, see functional description section. figure 11.typical -48v hotswap application circuit overcurrent protection (circuit breaker function) a sense resistor, placed in the supply path between v ee and sense (see figure 11) generates a voltage internal to the X80000. when this voltage exceeds 50mv an over current condition exists and an internal ?ircuit breaker trips, turning off the gate drive to the external fet. the actual over-current level is dependent on the value of the current sense resistor. for example a 20m ? sense resistor sets the over-current level to 2.5a. xicors X80000 provides a safety mechanism during insertion of the board into the back plane. during insertion of the board into the backplane large currents may be induced. in order to prevent premature shut down of the external fet, the X80000 allows for a choice of up to 4 times the overcurrent setting during insertion. after the pwrgd signal is asserted, the X80000 switches back to the normal overcurrent setting. the over-current threshold voltage during insertion can be changed from 50mv to 100mv, 150mv, or 200mv, by setting bits in control register cr4. after the power fet turns off due to an over-current condition, a retry circuit turns the fet back on after a delay of t sc_retry . if the over-current condition remains, the fet again turns off. this sequence repeats until the over-current condition is released. there are various other options that program the retry circuit to change the number of retries or to not retry. an optional output signal, f ar , indicates a failure after retry. for a more detail description of this operation see functional description section. 27 far failure after re-try (far ) output signal. failure after re-try (far ) is asserted after a number of retries. used for overcurrent and hardshort detection. 28 batt-on battery on input . this input signals that the battery backup (or secondary supply) is supplying power to the backplane. it has an internal pulldown resistor. (>10m ? typi- cal) 29 pwrgd power good output. this output pin en- ables a power module. 30 igq1 gate current quick select bit 1 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an ex- ternal fet. it has an internal pulldown re- sistor. (>10m ? typical) 31 igq0 gate current quick select bit 0 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an ex- ternal fet. it has an internal pulldown re- sistor. (>10m ? typical) 32 mrh manual reset input hot-side. pulling the mrh pin low initiates a gate pin reset (gate pin pulled low). the mrh signal must be held low for 5 secs (minimum). pin name description v dd X80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 return 100k -48v dc/dc converter dc/dc converter i inrush x80001 0.1? 100
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 16 of 35 X80000/x80001 ?preliminary information gate drive output slew rate (inrush current) control the gate output drives an external n-channel fet. the gate pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. the X80000 provides an i gate current of 50ua to provide on- chip slew rate control to minimize inrush current. this current is programmable from 10ua to 160ua (in 10ua steps) to allow the X80000 to support various load conditions. see figure 12 and figure 13. i gate is chosen to limit the inrush current and to provide the best charge time for a given load, while avoiding overcurrent conditions. the user programs the i gate current using four i gate control bits. for applications that require different ramp rates during insertion and start-up and operations modes, the X80000 provides two external pins, igq1 and igq0, that allow the user to switch to different gate currents on-the-? by selecting one of four pre- selected i gate currents. when igq0 and igq1 are left unconnected, the gate current is determined by the gate control bits. the other three settings are 10ua, 70ua and 150ua. typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 second. for a more detailed description of this operation see functional description section. drain sense and power good indicator the X80000 provides a drain sense and power good indicator circuit. the pwrgd signal asserts low when there is no overvoltage, no undervoltage, and no overcurrent condition, and as the voltage at the drain pin is less v ee +v drain . for a more detailed description of this operation see functional description section. power on reset and system reset with delay application of power to the X80000 activates a power on reset circuit that pulls the reset pin active. this signal, if used, provides several bene?s. figure 12.typical inrush with gate slew rate control figure 13.selecting i gate current for slew rate control on the gate pin. it prevents the system microprocessor from starting to operate with insuf?ient voltage. it prevents the processor from operating prior to stabilization of the oscillator. it allows time for an fpga to download its con?uration prior to initialization of the circuit. it prevents communication to the eeprom during unstable power conditions, greatly reducing the likelihood of data corruption on power up. the spor/reset circuit is activatived when all voltages are within speci?d ranges and the following time-out conditions are met: pwrgd and v1good , v2good , v3good , and v4good . the spor/reset circuit will then wait 100ms and assert the reset pin. the spor delay may be changed by setting the tpor bits in register cr2. the delay can be set to 100 ms, 500 ms, 1 second, or 5 seconds. for more information see functional description. (v) time (ms) pwrgd (v) drain (v) gate (a) i inrush v dd 15 0 a 10 a 5 0 a i g = 50 a i g = 10 a i g = 50 a
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 17 of 35 X80000/x80001 ?preliminary information manual reset and remote shutdown the manual reset option allows a hardware reset of either the gate control or the pwrgd indicator. these can be used to recover the system in the event of an abnormal operating condition. the remote shutdown feature of the X80000 allows smart power control remotely through the smbus. the host system can either override the control of the fet , thus turning it off, or it can remove the override. removing the override restarts the power up sequence. quad voltage monitoring X80000 monitors 4 voltage enable inputs. when the eni (i=1-4) input is detected to be below the input threshold, the output vigood (i = 1 to 4) goes active. the vigood signal is asserted after a delay of 100ms. this delay can be changed on each vigood output individually with bits in register cr3. the delay can be 100ms, 500ms, 1s and 5s. the vigood signal remains active until eni rises above threshold. for more information see functional description. flexible power sequencing of multiple power supplies the X80000 provides several circuits such as multiple voltage enable pins, programmable delays, and a power good signals that can be used to set up ?xible power sequencing schemes for downstream dc-dc supplies. below are two examples: 1) power up of dc-dc supplies in parallel sequencing using programmable delays on power good (see figure 14 and figure 15). several dc-dc power supplies and their respective power up start times can be controlled using the X80000 such that each of the dc-dc power supplies will start up following the issue of the pwrgd signal. the pwrgd signal is fed into the eni inputs to the X80000. when pwrgd is valid, the internal voltage enable inputs issue vigood signals after a time delay. the vigood signals control the on /off pins of the dc-dc supplies. in the factory default condition, each dc/dc converter is instructed to turn on 100ms after the pwrgd goes active. however, each vigood delay is individually selectable as 100ms, 500ms, 1s and 5s. the delay times are chaged via the smbus during calibration of the system. see functional description for more details. figure 14.parallel sequencing of dc-dc supplies-timing 2) power up of dc-dc supplies via relay sequencing using power good and voltage enables (see figure 16 and figure 17). several dc-dc power supplies and their respective power up start times can be controlled using the X80000 such that each of the dc-dc power supplies will start in a relay sequencing fashion. the 1st dc-dc supply will power up when pwrgd is low after a 100ms delay. subsequent dc-dc supplies will power up after the prior supply has reached its operating voltage. one way to do this is by using an external cpu supervisor (for example the xicor x40430) to monitor the dc-dc output. when the dc/dc voltage is good, the supervisor output signals the X80000 en1 input to sequence the next supply. an opto-coupler is recommended in this connection for isolation. this con?uration ensures that each subsequent dc-dc supply will power up after the preceding dc-dc supplys voltage output is valid. again, the X80000 offers programmable delays for each voltage enable input that is selectable via the smbus during calibration of the system. see functional description for more details. pwrgd eni t delayi vigood on /off i = 1 to 4 programmable delay dc-dc supply #i on timing not to scale example: 1 to 4 independent dc-dc supplies. sequence started in parallel by pwrgd . individual dc/dc supplies controlled via vigood signals 100ms 500ms 1 sec 5 secs choose different delays for each voltage controlled eni valid
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 18 of 35 X80000/x80001 ?preliminary information figure 15.typical application of hotswap and dc-dc parallel power sequencing. v dd v3good en3 v2good en2 v1good en1 pwrgd X80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% on /off c3 0.1? 100v c4 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 reset c v cc1 3.3v gnd on /off c6 0.1? 100v c7 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 fpga v cc1 2.5v gnd on /off c9 0.1? 100v c10 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 asic v cc1 1.8v gnd r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 c5 100? 16v c8 100? 16v c11 100? 16v + + + v4good en4 on /off c12 0.1? 100v c13 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v gnd c14 100? 16v + reset opto coupler pwrgd reset v cc2 v cc2 v cc2 mrh mrc return 100k opto coupler x80001 0.1? 100
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 19 of 35 X80000/x80001 ?preliminary information figure 16.relay sequencing of dc-dc supplies. (timing) reset (x40430) en2 pwrgd en1 t delay1 v1good on /off1 en1 valid dc-dc supply #1 on dc-dc#1 x40430 vmon threshold en2 valid dc-dc supply #2 on v2good timing not to scale example: two independent dc-dc supplies in relay timing 100ms on /off2 programmable delay programmable delay output 500ms 1sec 5sec 100ms 500ms 1sec 5sec dc-dc#2 output t delay2
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 20 of 35 X80000/x80001 ?preliminary information figure 17.typical application of hotswap and dc-dc relay sequencing v dd v3good en3 v2good en2 v1good en1 pwrgd X80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% on /off c3 0.1? 100v c4 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 3.3v gnd on /off c6 0.1? 100v c7 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 2.5v gnd on /off c9 0.1? 100v c10 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.8v gnd r4 182k 1% r6 10k 1% q1 irfr120 c5 100? 16v c8 100? 16v c11 100? 16v + + + v4good en4 on /off c12 0.1? 100v c13 100? 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v gnd c14 100? 16v + reset opto coupler reset x40430 opto coupler vmon<1:3> vfail<1:3> pwrgd reset c v cc1 fpga v cc1 asic v cc1 v cc2 v cc2 v cc2 mrh mrc r5 30k 1% return 100k opto coupler x80001 (optional) 0.1? 100
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 21 of 35 X80000/x80001 ?preliminary information functional description programmable overvoltage and undervoltage block as shown in figure 20, this circuit block contains comparators and programmable voltage references to monitor for a single overvoltage and dual undervoltage trip points. xicor has programmed the overvoltage and undervoltages trip points as shown in table 1 below in manufacturing. table 1. overvoltage/undervoltage default thresholds a resistor divider connected between the plus and minus input voltages and the v uv/ov pin (see figure 18) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. using the thresholds in table 1 and the equations of figure 18 the desired operating voltage can be determined. figure 19 shows the resistance values for various operating voltages. figure 18.overvoltage undervoltage divider figure 19.operating voltage vs. resistor ratio battery back up operations an external signal, batt-on is provided to switch the undervoltage trip point. the batt-on signal is a logic high if v ihb > v ee + 4v and is a logic low if v ilb < v ee + 2v. the time from a batt-on input change to a valid new undervoltage threshold is 100ns. see electrical speci?ations for more details. note: the v uv/ov pin must be limited to less than v ee + 5.5v in worst case conditions. values for r1 and r2 must be chosen such that this condition is met. xicor recommends r1 = 182k ? and r2 = 10k ? to conform to factory settings. table 2. selecting between undervoltage trip points overvoltage/undervoltage fault condition flags on any overvoltage or undervoltage violation, the X80000 cuts- off the gate. this condition also sets the fault-overvoltage (fov) or fault-undervoltage1/2 (fuv1/2) bits low. these bits are readable through the smbus. to clear the fault bits, the fault condition must ?st be recti?d (by the system) then cleared by a write to fault detection register. please refer to fdr section on page 27. see table 2. table 3. overvoltage/undervoltage flag bits threshold symbol description falling rising max/min voltage 1 lockout voltage 2 v ov overvoltage (X80000) 3.87v 3.9v 74.3 74.9 v ov overvoltage (x80001) 3.51v 3.54v 67.4 68 v uv1 undervoltage 1 2.21v 2.24v 43.0 42.4 v uv2 undervoltage 2 1.73v 1.76v 33.8 33.2 notes: 1: max/min voltage is the maximum and mimimum operat- ing voltage assuming the recommended v uv/ov resistor divider. 2: lockout voltage is the voltage where the X80000/1 turns off the fet. r1 r2 v p v uv/ov v n voltage divider: or: v uv ov ? v s r 2 r 1 r 2 + ------------------- - ?? ?? = v s v uv ov ? r 1 r 2 + r 2 ------------------- - ?? ?? = v s pin description trip point selection batt-on undervoltage trip point selection pin if batt-on = 0, v uv1 trip point is selected; if batt-on = 1, v uv2 trip point is selected. v uv1 and v uv2 are undervoltage thresholds. symbol violation (on) normal (off) fov fov = 0, when v uv/ov > v ov (overvoltage) fov = 1, when v uv/ov < v ov + 0.2v and reset by a write operation fuv1/2 fuv1/2 = 0, when v uv/ov < v uv1/2 (undervoltage) fuv1/2 = 1, when v uv/ov > v uv1/2 - 0.2v and reset by a write operation batt-on = v ee v ov v uv1 v uv2 operating voltage batt-on = v rgo 100 90 80 70 60 50 40 30 20 10 0 150 158 166 175 182 190 198 206 214 222 operating voltage (volts) r1 in kohms (for r2=10k)
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 22 of 35 X80000/x80001 ?preliminary information figure 20.programmable undervoltage and overvoltage for primary and battery backup overcurrent protection (circuit breaker function) the X80000 over-current circuit provides the following functions: over-current shut-down of the power fet and external power good indicators. noise ?tering of the current monitor input. relaxed over-current limits for initial board insertion. over-current recovery retry operation. flag of over-current fault condition. flag of over-current retry failure. over-current shut-down as shown in figure 21, this circuit block contains a resistor ladder, a comparator, a noise ?ter and a programmable voltage reference to monitor for over-current conditions. the overcurrent voltage threshold (v oc ) is 50mv. this can be factory set, by special order, to any setting between 30mv and 100mv. v oc is the voltage between the sense and v ee pins and across the r sense resistor. if the selected sense resistor is 20mw, then 50mv corresponds to an overcurrent of 2.5a. if an over-current condition is detected, the gate is turned off, all power good indicators go inactive and an over-current failure bit (foc) is set. overcurrent noise filter the X80000 has a noise (low pass) ?ter built into the over- current comparator. the comparator will thus ignore current spikes shorter than 5?. other ?ter options are provided by setting control bits in register cr4. the control bits set the comparator to ignore current spikes shorter that 5?, 10? or 20? and allow the ?ter to be turned off. table 4. noise filter for over currents over-current during insertion insertion is de?ed as the ?st plug-in of the board to the backplane. in this case, the X80000 is initially fully powered off prior to the hot plug connection to the mains supply. this condition is different from a situation where the mains supply has temporarily failed resulting in a partial recycle of the power. this second condition will be referred to as a power cycle. during insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. to prevent the over-current sensor from turning off the fet inadvertently, the X80000 has the ability to allow more current to ?w through the powerfet and the sense resistor for a short period of time until the fet turns on and the pwrgd signal goes active. in the standard setting, 200mv is allowed across sense resistor the during insertion (10a assuming a 20mw reistor). two bits in register cr4 select the programmable voltage reference control & status registers 2:1 mux -48v v uv/ov batt_on sda scl overvoltage flag undervoltage flag_1 undervoltage flag_2 undervoltage flag r1=182k r2=10k v ov to gate control to gate control fault bits fov fuv1/2 + - - + - + programmable voltage reference programmable voltage reference v uv1 v uv2 smbus f1 f0 t nf (maximum noise input pulse width) 0 0 0? 0 1 5? 1 0 10? 1 1 20?
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 23 of 35 X80000/x80001 ?preliminary information insertion current limit of 1x, 2x, 3x or 4x the base setting of 50mv. this provides a mechanism to reduce insertion issues associated with huge current surges. table 5. insertion over-current threshold options hardshort protection - programmable retry in the event on an over-current or hard short condition, the X80000 includes a retry circuit. this circuit waits for 100ms, then attempts to again turn on the fet. if the fault condition still exists, the fet turns off and a retry counter (sc_counter) increments. after four failed trys, the X80000 sets a failed after retry status (far_stat) fault bit, sets the f ar pin low and goes into an idle state. in this state the gate pin will not go active until the device is cleared. the retry circuit can be programmed to handle the retry operation in one of eight ways (see table 6). the options allow retries from zero to unlimited and speci?s when to assert the f ar (failure after re-try) signal. in the ?lways retry case there is no idle state, so when the over-current condition clears, the gate goes active and the fet turns on. there are four optional retry delay periods. these are 100ms, 500ms, 1s, and 5s. these are programmed by bits located in the cr2 register. after f ar is asserted, there are two ways to clear the hardshort protection: 1 master reset hot side. the master reset pin, mrh , can be asserted by pulling it low. upon mrh assertion, all default values are restored and the retry is cleared. 2) power cycle the part, turning v dd off, then on. if an overcurrent condition does not occur on any retry, the gate pin will proceed to open at the user de?ed slew rate. overcurrent fault condition flags on any overcurrent violation, the X80000 will cut-off the gate, turning off the voltage to the load, and setting all power good pins to their disabled state. in this condition, the fault-over- current bit (foc) goes low. to clear foc, remove the over current condition, then write to the control register. refer to instructions on writing to the fdr. see table 8. when exceeding the overcurrent retry limit, the status bit ?ar_stat is set to ? and the f ar pin is asserted. to clear far_s tat, w r ite to the control register. refer to instructions on writing to the fdr. see table 9. table 6. retry and event sequence options table 7. retry event delay options table 8. overcurrent flag bit table 9. retry count failure status bit vs1 vs0 v oci 0 0 50mv (1x) 0 1 100mv (2x) 1 0 150mv (3x) 1 1 200mv (4x) nr2 nr1 nr0 n retry and retry sequence of events (failure mode) 0 0 0 always retry, do not assert far pin (default) 001n retry = 1 (one retry), assert far pin after n retry, stop retry, and shutoff gate pin 010n retry = 2 (two retries), assert far pin after n retry, stop retry, and shutoff gate pin 011n retry = 3 (three retries), assert far pin after n retry, stop retry, and shutoff gate pin 100n retry = 4 (four retries), assert far pin after n retry, stop retry, and shutoff gate pin 101n retry = 5 (five retries), assert far pin after n retry, stop retry, and shutoff gate pin 1 1 0 always retry, assert far pin after 1st retry; clear far when foc cleared, do not shutoff gate pin. 111n retry = 0 (no retry), asset far , and shutoff gate pin. tsc1 tsc0 t sc_retry , delay between retries 0 0 100 miliseconds 0 1 500 miliseconds 1 0 1 second 1 1 5 seconds status bit violation (on) normal (off) foc foc = 0, when v rsense > v oc foc = 1, when: ? rsense < v oc - 0.2v and reset by a write operation or hardshort retry is initiated. status bit condition far_stat if far_stat = 1, far is asserted. if far_stat = 0, far is deasserted
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 24 of 35 X80000/x80001 ?preliminary information figure 21.overcurrent detection/short circuit protection with programmble retry and flag monitors. programmable slew rate (gate) control as shown in figure 22, this circuit block contains a selectable current source (i gate ) that drives the 50ua current into the gate pin. this current provides a controlled slew rate for the fet. X80000 allows the user to chage the gate current to one of sixteen possible i gate values. the options allow currents of between 10 a to 160 a in 10 a increments. once the overcurrent condition and the amount of load is known, an appropriate slew rate can be determined and selected for the external fet. this will ensure proper operation to control inrush currents during hot insertion modes. software slew rate control users can adjust the slew rate control by using an smbus write command to change the slew rate control bits. this allows adaptation in the case of changing load conditions, creates a modular design for downstream dc-dc supplies, and provides control of the load on the hot voltage when slew rates vs. loads vary. gate current quick selection for applications that require different ramp rates during insertion and start-up and operations modes or those where the serial interface is not available, the X80000 provides two external pins, igq1 and igq0, that allow the system to switch to different gate current on-the-? with pre-selected i gate currents. the igq1 and igq0 pins can be used to select from one of four set values. table 10. i gate output current options . typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 second. 2 bit noise filtering control registers sda scl overcurrent logic and gate control bl ock short-circuit retry logic and system monitors far failure after re-try retry delay retry counter n retry fault bit far_stat programmable voltage reference 0? 5? 10? 20? 36r 4x 3x 2x 1x r r r r + -48v overcurrent event r sense smbus v ee ig3 ig2 ig1 ig0 i gate ( a) 0000 10 0001 20 0010 30 0011 40 0100 50 default 0101 60 0110 70 0111 80 1000 90 1001 100 1010 110 1011 120 1100 130 1101 140 1110 150 1111 160 igq1 pin igq0 pin contents 0 0 defaults to gate current set by ig3:ig0 bits 0 1 gate current is 10 a 1 0 gate current is 70 a 1 1 gate current is 150 a
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 25 of 35 X80000/x80001 ?preliminary information figure 22. programmble slew rate (inrush current) control gate capacitor/filtering no external gate capacitor is required by the X80000 series of devices. however, there may be applications in which the combination of load and surge current limits result in a large number of retries. to reduce the number of retries, an external capacitor from the fet gate to v ee can be used. this capacitor shunts to v ee the current ?wing through the (initially uncharged) cgs capacitance of the fet. this prevents an initial rise in the gate voltage during turn on of the fet, thus reducing the inrush current. this will minimize the number of retries when the fet is being turned on. the size of the capacitor will vary based on the load, the choice of fet, the gate current and the desired maximum surge current. the use of a 0.1? capacitor covers most fet types. the surge current can then be controlled by using the slew rate control bits (ig0?g3 in register 2) or the igq0 and igq1 pins. the use of a series resistor in the gate lead is intended to prevent high frequency oscillations. drain sense and power good indicator as shown in figure 23, this circuit block contains a drain sense voltage trip point ( ? ? ? ? v drain ), a comparator, and an internal voltage reference. these provide a drain sense circuit to determine the whether the fet has turned on as requested. if so, the power good indicator (pwrgd ) goes active. the drain sense circuit checks the drain pin. if the voltage on this pin is greater that 1v above v ee , then a fault condition exists. the pwrgd signal assert (logic low) only when all of the below conditions are true: there is no overvoltage or no undervoltage condition, (i.e. undervoltage < v ee < overvoltage.) there is no overcurrent condition (i.e. v ee - v sense < v oc .) the fet is turned on (i.e. v drain < v ee + 1v) figure 23.drain sense and power good indicator power on/system reset and delay once the pwrgd signal is asserted, the power sequencing of the dc-dc modules can commence. reset will go active 100ms after all vigood (i=1 to 4) outputs are asserted. this delay time can be changed by setting bits in register cr2. see figure 24. table 11. spor reset delay options figure 24. power on/system reset and delay (block diagram) sense v ee r sense load v dd =12v slew selection gate 10? i inrush drain 100k gate current igq1 igq0 -48v control registers sda scl smbus to 160? logic rate quick select logic 100* 10nf* * optional components see section ?ate capacitor/filtering tpor1 tpor0 t spor delay before reset assertion 0 0 100 miliseconds (default) 0 1 500 miliseconds 1 0 1 second 1 1 5 seconds (factory programmable) sense v ee r sense load gate drain 100k -48v sda scl smbus pwrgd + 3v v ee control/status registers power good logic control registers eeprom 2kbits reset logic spor mrc sda v dd drain sense & power good logic enable logic t spor delay reset pwrgd vigood i = 1 to 4 p bus interface scl v ee remote & fault
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 26 of 35 X80000/x80001 ?preliminary information voltage enable pins as shown in figure 25, this circuit block contains four separate voltage enable inputs, a time delay circuit, and an output driver. the four voltage enable inputs (en1 , en2 , en3 , en4 ) track secondary voltage levels and assert the voltage good signal pins (v1good , v2good , v3good , v4good ) if the enable voltages are below the input threshold voltage (typical 2.5v). when the eni input goes low, the vigood signal goes low after a (default) delay of 100ms. the delay times may be individually changed using control bits in register cr3. the voltage good signals (vigood ) will remain active low until the enable input (eni ) goes above the input threshold. table 12. vigood output time delay options figure 25.voltage enable control and vgood outputs manual reset (hot side and cold side) the X80000 has two manual reset pins: mrh (manual reset hot side) and mrc (manual reset cold side). the mrh signal is used as a manual reset for the gate pin. this pin is used to initiate soft reinsert. when mrh is pulled low the gate pin will be pulled low. it also clears the remote shutdown register (rsr) and the f ar signal. when the mrh pin goes high, it removes the override signal and the gate will turn on based on the selected gate control mechanism. table 13. manual reset of the hot side (gate signal) the mrc signal is used as a manual reset for the pwrgd signal. this pin is used to initiate a soft restart. when the mrc is pulled high, the pwrgd signal is pulled high. when mrc pin goes low, the pwrgd pin goes operational. it will go low if all constraints on the gate are within limits. table 14. manual reset of the cold side (pwrgd signal) fault detection the X80000 contains a fault detection register (fdr) that provides the user the status of the causes for a reset pin active (see table 17). at power-up, the fdr is defaulted to all ?? the system needs to initialize the register to all ? before the actual monitoring can take place. in the event that any one of the monitored sources fail, the corresponding bit in the register changes from a ? to a ? to indicate the failure (vigood sources set the bit low when the vigood goes low indicating a ?ood status). when a reset is detected by the main controller, the controller should read of the fdr and note the cause of the fault. after reading the register, the controller can reset the register bit back to all ? in preparation for future monitored conditions. tid1 tid0 t delayi 0 0 100ms 0 1 500ms 1 0 1 secs 1 1 5 secs where i is the ith voltage enable (i = 1 to 4). en1 en2 en3 en4 v4good v3good v2good v1good delay logic enable logic v ee v trip1 v trip2 v trip3 v trip4 control registers smbus interface time delay 1 time delay 2 time delay 3 time delay 4 mrh gate pin requirements 1 operational when mrh is high the manual reset (hot) function is disabled 0 off mrh must be held low minimum of 5 secs mrc pwrgd requirements 1 high mrc must be held high minimum of 5 secs 0 operational when mrc is low the mrc function is disabled
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 27 of 35 X80000/x80001 ?preliminary information remote shutdown the gate of the external mosfet can be remotely shutdown by using a software command sequence. a byte write of ?0101010 (aah) data to the remote shutdown register (rsr) will shutdown the gate and the gate will be pulled low. activating the mrh pin or a writing 00h into the rsr will turn off the override signal and the gate will turn on based on the gate control mechanism. the rsr powers up with ?s in the register and its contents are volatile. control registers and memory the user addressable internal control, status and memory components of the X80000 can be split up into four parts: control register (cr) fault detection register (fdr) remote shutdown register (rsr) eeprom array registers the control registers, remote shutdown register and fault detection register are summarized in table 15. changing bits in these registers change the operation of the device or clear fault conditions. reading bits from these registers provides information about device con?uration or fault conditions. reads and writes are done through the smbus serial port. it is important to remember that, in most cases, the smbus serial port must be isolated between the X80000, which is referenced to -48v, and the system controller, which is referenced to ground. all of the control register bits are nonvolatile (except for the wel bit), so they do not change when power is removed. the values of the register block can be read at any time by performing a random read (see serial interface) at the speci? byte address location. only one byte is read by each register read operation. bits in the registers can be modi?d by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. table 15. register address map byte addr. register name description bit memory type 76543210 00h cr0 control register 0 wel0000000 volatile 01h cr1 control register 1 wpen 0 0 bp1 bp0 nr2 nr1 nr0 eeprom 02h cr2 control register 2 ig3 ig2 ig1 ig0 tpor1 tpor0 tsc1 tsc0 eeprom 03h cr3 control register 3 t4d1 t4d0 t3d1 t3d0 t2d1 t2d0 t1d1 t1d0 eeprom 04h cr4 control register 4 vs1vs0f1f00000 eeprom 05h rsr (1) remote shutdown register aah: override fet control and shutdown the fet 00h: turn off override (all other data combinations to rsr are reserved.) volatile ff fdr fault detection register fov fuv1/2 foc far_ stat v40s v30s v20s v10s volatile (1) this register is write only
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 28 of 35 X80000/x80001 ?preliminary information table 16. hardware/software control and fault detection bits summary symbol location(s) control function/ status indication description register bits software control bits f0 f1 cr4 5:4 insertion current filter f1=0, f0=0 ; t nf = 0 f1=0, f0=1 ; t nf = 5? f1=1, f0=0 ; t nf = 10? f1=1, f0=1 ; t nf = 20? ig0 ig1 ig2 ig3 cr2 7:4 gate current select see table 10 on page 24 nr0 nr1 nr2 cr1 2:0 retry sequence options see table 6 on page 23 t1d0 t1d1 cr3 1:0 v1good time delay tid1=0, tid0=0 : vigood delay = 100ms tid1=0, tid0=1 : vigood delay = 500ms tid1=1, tid0=0 : vigood delay = 1s tid1=1, tid0=1 : vigood delay = 5s t2d0 t2d1 cr3 3:2 v2good time delay t3d0 t3d1 cr3 5:4 v3good time delay t4d0 t4d1 cr3 7:6 v4good time delay tpor0 tpor1 cr2 3:2 reset delay time tpor1=0, tpor0=0 : reset delay = 100ms tpor1=0, tpor0=1 : reset delay = 500ms tpor1=1, tpor0=0 : reset delay = 1s tpor1=1, tpor0=1 : reset delay = 5s tsc0 tsc1 cr2 1:0 overcurrent retry delay time tsc1=0, tsc0=0 ; t sc_retry = 100ms tsc1=0, tsc0=1 ; t sc_retry = 500ms tsc1=1, tsc0=0 ; t sc_retry = 1s tsc1=1, tsc0=1 ; t sc_retry = 5s vs0 vs1 cr4 7:6 insertion overcurrent limit vs1=0, vs0=0 ; insertion overcurrent limit = 1x vs1=0, vs0=1 ; insertion overcurrent limit = 2x vs1=1, vs0=0 ; insertion overcurrent limit = 3x vs1=1, vs0=1 ; insertion overcurrent limit = 4x wel cr0 7 write enable wel = 1 enables write operations to the controi registers and eeprom. wel = 0 prevents write operations. wpen cr1 7 write protect wpen = 1 (and wp pin high) prevents writes to the control registers and the eeprom. bp1 bp0 cr1 4:3 eeprom block protect bp1=0, bp0=0 : no eeprom memory protected. bp1=0, bp0=1 : upper 1/4 of eeprommemory protected bp1=1, bp0=0 : upper 1/2 of eeprom memory protected. bp1=1, bp0=1 : all of eeprom memory protected. hardware select bits igq0 igq1 input pins gate current select igq1=0, igq0=0 : i gate = set by ig0-ig3 igq1=0, igq0=1 : i gate = 10? igq1=1, igq0=0 : i gate = 70? igq1=1, igq0=1 : i gate = 150? batton input pin main or battery batton = 0 ; undervoltage threshold = v uv1 batton = 1 ; undervoltage threshold = v uv2
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 29 of 35 X80000/x80001 ?preliminary information memory the X80000 contains a 2kbit eeprom memory array. this array can contain information about manufacturing location and dates, board con?uration, fault conditions, service history, etc. access to this memory is through the smbus serial port. read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. a single read command can return the entire contents of the eeprom memory. register and memory protection in order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80000. these are a write enable latch, block protect bits, a write protect enable bit and a write protect pin. wel: write enable latch a write enable latch (wel) bit controls write accesses to the nonvolatile registers and the eeprom memory array in the X80000. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address (registers or memory) will be ignored. the wel bit is set by writing a ? to the wel bit and zeroes to the other bits of the control register 0 (cr0). it is important to write only 00h or 80h to the cr0 register. once set, wel remains set until either it is reset to 0 (by writing a ? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. note, a write to fdr or rsr does not require that wel=1. bp1 and bp0: block protect bits the block protect bits, bp1 and bp0, determines which blocks of the memory array are write protected. a write to a protected block of memory is ignored. the block protect bits will prevent write operations to one of four segments of the array. wpen: write protect enable the write protect pin and write protect enable bit in the cr1 register control the programmable hardware write protect feature. hardware protection is enabled when the wp pin is high and wpen bit is high and disabled when wp pin is low or the wpen bit is low. when the chip is hardware write protected, non-volatile writes to all control registers (cr1, cr2, cr3, and cr4) are disabled including bp bits, the wpen bit itself, and the blocked sections in the memory array. only the section of the memory array that are not block protected can be written. table 17. fault detection bits summary symbol location(s) control function/ status indication description register bits far_stat fdr 4 retry violation far_stat = 0 : failure after retry detected (must be preset to 1). foc fdr 5 overcurrent violation foc = 0 : over current detected (must be preset to 1). fov fdr 7 overvoltage violation fov = 0 : over voltage detected (must be preset to 1). fuv1/2 fdr 6 undervoltage violation fuv1/2 = 0 : under voltage detected (must be preset to 1). v1os fdr 0 1st voltage good v1os = 0 : v1good pin has been asserted (must be preset to 1). v2os fdr 1 2nd voltage good v2os = 0 : v2good pin has been asserted (must be preset to 1). v3os fdr 2 3rd voltage good v3os = 0 : v3good pin has been asserted (must be preset to 1). v4os fdr 3 4th voltage good v4os = 0 : v4good pin has been asserted (must be preset to 1). bp1 bp0 protected addresses (size) array lock 0 0 none (default) none (default) 0 1 c0h - ffh (64 bytes) upper 1/4 1 0 80h - ffh (128 bytes) upper 1/2 1 1 00h - ffh (256 bytes) all table 18. write protect conditions wel wp wpen memory array not block protected memory array block protected writes to cr1, cr2, cr3, cr4 protection low x x writes blocked writes blocked writes blocked hardware high low x writes enabled writes blocked writes enabled software high high low writes enabled writes blocked writes enabled software high high high writes enabled writes blocked writes blocked hardware
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 30 of 35 X80000/x80001 ?preliminary information bus interface information interface conventions the device supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 26. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. see figure 27. the device will respond with an acknowledge after recognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identi?r and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. figure 26.valid start and stop conditions figure 27.acknowledge response from receiver device addressing addressing protocol overview depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 byte protocol is used. all operations however must begin with the slave address byte being clocked into the smbus port on the scl and sda pins. the slave address selects the part of the device to be addressed, and speci?s if a read or write operation is to be performed. slave address byte following a start condition, the master must output a slave address byte. this byte consists of three parts: the device type identi?r which consists of the most sig- ni?ant four bits of the slave address (sa7 - sa4). the device type identi?r must be set to 1010 in order to select the device. the next two bits (sa3 - sa2) are slave address bits. the bits received via the smbus are compared to a0 and a1 pins and must match or the communication is aborted. the next bit, sa1, selects the device memory sector. there scl sda start stop data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 31 of 35 X80000/x80001 ?preliminary information are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. the least signi?ant bit of the slave address (sa0) byte is the r/w bit. this bit de?es the operation to be per- formed. when the r/w bit is ?? then a read operation is selected. a ? selects a write operation (refer tofigure 28). figure 28.slave address format serial write operations in order to perform a write operation to either a control register or the eeprom array, the write enable latch (wel) bit must ?st be set. writes to the wel bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. a write to a protected block of memory will suppress the acknowledge bit. page write the device is capable of a page write operation. see figure 29. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?olls over and goes back to ? on the same page. see figure 30. this means that the master can write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the ?st 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. afterwards, the address counter would point to location 6 of the page that was just written. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. the contents of the array will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indicate the end of the masters byte load operation, the device initiates the internal high voltage cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. see figure 33. sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read / sa4 r/w 101 0 write address external device memory select a1 a0 ms internal address (sa1) internally addressed device 0 eeprom array 1 control register, fault detection register, remote shutdown register bit sa0 operation 0 write 1 read
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 32 of 35 X80000/x80001 ?preliminary information figure 29.page write operation figure 30.writing 12 bytes to a 16-byte page starting at location 10 figure 31.random address read sequence figure 32.current address read sequence s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 to n to 16) 1010 address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 1010 1010 s t a r t s t o p slave address dat a sda bus signals from the slave signals from the master 1 a c k 1010
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 33 of 35 X80000/x80001 ?preliminary information figure 33.acknowledge polling sequence serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, random reads, and sequential reads. random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 31 for the address, acknowledge, and data transfer sequence. current address read internally the device contains an address counter that maintains the address of the last word read incremented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power up, the address of the address counter is unde?ed, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. see figure 32 or the address, acknowledge, and data transfer sequence. operational notes the device powers-up in the following state: the device is in the low power standby state. the wel bit is set to ?? in this state, it is not possible to write to the device. sda pin is the input mode. reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: the wel bit must be set to allow write operations. the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. a two step sequence is required before writing into the control register to change array settings. the wp pin, when held high, prevents all writes to the array and all the register. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes
rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 34 of 35 X80000/x80001 ?preliminary information packaging information 0.009 (0.23) 0.015 (0.38) 0.185 (4.70) 0.271 (6.90) 0.279 (7.10) 0.014 (0.35) 0.029 (0.75) (4.70) 0.185 (4.70) 0.027 (0.70) 0.031 (0.80) 0.000 (0.00) 0.030 (0.76) 0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05) 0.271 (6.90) 0.279 (7.10) 0.271 (6.90) 0.279 (7.10) pin 1 indent 32-lead very very thin quad flat no lead package 7mm x 7mm body with 0.65mm lead pitch
X80000/x80001 ?preliminary information ?icor, inc. 2001 patents pending limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. copyrights and trademarks xicor, inc., the xicor logo, e 2 pot, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, identiprom, e 2 key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and produc t names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. rev 2.8 10/15/02 www.xicor.com characteristics subject to change without notice 35 of 35

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